1. Field of the Invention
This invention relates to a semiconductor device using a hybrid wafer having an SOI (Silicon On Insulator) region and a bulk region and a manufacturing method thereof.
2. Description of the Related Art
Recently, various attempts for lowering the parasitic capacitance, lowering the power consumption of a logic circuit and enhancing the operation speed of the logic circuit have been made by using a thin film SOI (Silicon On Insulator) wafer instead of the conventional silicon wafer and forming elements on the SOI wafer. Further, microprocessors using the SOI wafers have been commercialized. In the future, it is predicted that the necessity for a system LSI using the above SOI logic as a core is increased.
However, since the potential of a body region in which the channel of a MOSFET on the SOI wafer is formed is set into an electrically floating state, a variation in the threshold voltage occurs and a leakage current caused by the circuit operation occurs due to the so-called floating body effect. Therefore, it is not suitable to apply the SOI wafer to a circuit such as cell transistors of a DRAM or paired transistors of a sense amplifier circuit or analog circuit which has a severe specification for a leakage current level or matching characteristic.
In order to solve the above problem, it is proposed to prepare a hybrid wafer having a bulk region formed on the SOI wafer and form a circuit such as a DRAM which is not suitable for the SOI wafer on the bulk region. More specifically, the following methods are provided, for example.
First, a method for selectively forming an SOI region on the bulk wafer by use of an SIMOX (Separation by IMplantation of Oxygen) using a mask pattern is provided (refer to “Jpn. Pat. Appln. KOKAI Publication No. 10-303385” and “Robert Hannon, et al., 2000 Symposium on VLSI Technology of Technical Papers, pp. 66-67”).
Second, a method for laminating a wafer on a bulk wafer having a patterned insulating film thereon is provided (refer to Jpn. Pat. Appln. KOKAI Publication No. 8-316431).
Third, a method for selectively and partially etching and removing an SOI layer on the SOI wafer and a buried insulating film formed therein is provided (refer to Jpn. Pat. Appln. KOKAI Publication No. 7-106434, Jpn. Pat. Appln. KOKAI Publication No. 11-238860, and Jpn. Pat. Appln. KOKAI Publication No. 2000-91534).
Fourth, a method for depositing silicon on a supporting substrate of a bulk region by a selective epitaxial growth method and making the silicon layer flat by polishing as required in order to eliminate the difference in level caused between the SOI region and the bulk region in the third method is provided (refer to “Jpn. Pat. Appln. KOKAI Publication No. 2000-243944” and “T. Yamada, et al., 2002 Symposium on VLSI Technology of Technical Papers, pp. 112-113”).
In the above various methods using the hybrid wafer, the fourth method is excellent in productivity of elements since the difference in level between the element surface of the SOI region and the element surface of the bulk region is eliminated. Further, the fourth method is a method which can flexibly cope with a case wherein the film thickness of the SOI layer or buried insulating film varies or the material of the SOI layer such as a silicon layer or SiGe layer is changed since a semiconductor device is manufactured by use of a ready-made SOI wafer.
However, the fourth method has a problem as described below. Before explaining the problem, the fourth method is specifically explained below.
First, as shown in FIG. 41, an SOI wafer having a supporting substrate 111, buried insulating film 112 and SOI layer 113 is prepared.
Then, as shown in FIG. 42, a first mask member (for example, SiN film) 114 is formed on the SOI layer 113 to protect the same. Next, the first mask member 114, SOI layer 113 and buried insulating film 112 in the bulk region are selectively etched and removed in this order. At this time, a thin buried insulating film 112′ is left behind on the supporting substrate 111.
After this, as shown in FIG. 43, a second mask member (for example, SiN film) 116 for protection of the side wall of the SOI layer 113 is formed on the entire surface. Then, a spacer formed of the second mask member 116 is formed on the side surface of the SOI layer 113 by an anisotropic dry-etching process. At this time, as in the step shown in FIG. 42, a thin buried insulating film 112″ is left behind on the supporting substrate 111.
Next, as shown in FIG. 44, the buried insulating films 112, 112″ are removed by using an HF solution or the like without giving damage to the supporting substrate 111. In this case, since the mask members 114, 116 on the upper portion and side surface of the SOI layer 113 are insulating films of a type different from that of the buried insulating film 112, the mask members 114, 116 can be left behind even if the buried insulating films 112, 112″ are removed.
Then, as shown in FIG. 45, an epitaxial layer 117 is formed as an element forming film of single crystal silicon or the like on an exposed portion of the supporting substrate 111 by use of the epitaxial growth technique. The epitaxial growth process is performed to adjust the heights of the upper surface of the epitaxial layer 117 and the upper surface of the SOI layer 113 so as to set the upper surface of the epitaxial layer 117 and the upper surface of the SOI layer 113 substantially equal in height to each other. In this case, a facet 161 is formed on the upper end portion of the epitaxial layer 117 which lies on the SOI region side.
Next, as shown in FIG. 46, the first mask member 114 is removed. At this time, the second mask member 116 formed on the side surface of the SOI layer 113 is removed together with the first mask member 114 since the second mask member 116 is formed of the same material as that of the first mask member 114. As a result, a concave portion 160 is formed in the boundary portion between the SOI region and the bulk region.
Then, as shown in FIG. 47, gate insulating films 120, 121, gate electrodes 122, 123, 131, and element isolation regions 118, 119, 130 of the STI (Shallow Trench Isolation) structure are formed.
With the fourth method of the prior art, the facet 161 and concave portion 160 are formed in the boundary portion between the SOI region and the bulk region. Therefore, in order to eliminate the facet 161 and concave portion 160, the space for the element isolation region 130 in the boundary portion between the SOI region and the bulk region is made large.